CSci 330: Verilog examples

Incr8

module Incr8 (In, Out, Carry);
    input [7:0] In;
    output [7:0] Out;
    output Carry;

    assign Out = In + 1;
    assign Carry = In == 255;
endmodule

Incr16

`include "Incr8.v"
module Incr16 (In, Out, Carry);
    input [15:0] In;
    output [15:0] Out;
    output Carry;

    wire [7:0] LOut;
    wire [7:0] UOut;
    wire LCarry;
    wire UCarry;

    Incr8 lower(In[7:0], LOut, LCarry);
    Incr8 upper(In[15:8], UOut, UCarry);

    assign Carry = LCarry && UCarry;
    assign Out = { LCarry ? UOut : In[15:8], LOut };
endmodule

Counter8

module Counter8 (Clock, Cur);
    input Clock;
    output [7:0] Cur;
    reg [7:0] Count;

    assign Cur = Count;

    initial begin
        Count = 0;
    end

    always @(posedge Clock) begin
        Count = Count + 1;
    end
endmodule